1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a controlling method thereof, more particularly, to a semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, and a controlling method of the semiconductor memory device.
2. Description of the Related Art
Recently, there have been increasing demands for a system LSI having a logic circuit and a memory mounted on a same substrate. Examples of the memory used in the system LSI are a flash memory, a dynamic random access memory (DRAM), a ferroelectric memory (FRAM), etc.
Among these, the flash memory is nonvolatile, and thus provides good process consistency with a MOS field-effect transistor. Therefore, the flash memory is suitable to be mounted on a same substrate with a logic circuit. However, the flash memory is incapable of writing or erasing data at high speed. Hence, when there is a need of writing or erasing data at high speed, the DRAM or the FRAM has to be mounted on the same substrate with a logic circuit. However, since the DRAM and the FRAM comprise a highly dielectric material, a ferroelectric material, or special electrode material, etc., the DRAM or the FRAM provides ill process consistency with a logic circuit.
To solve the abovementioned problem, Japanese Laid-Open Pat. App. No. 2000-150680 discloses a direct tunnel memory (DTM) as a device providing good process consistency with a logic circuit and capable of writing and erasing data at high speed. FIG. 1 is a cross-sectional view of a structure of this direct tunnel memory (DTM). As shown in FIG. 1, each memory cell of the DTM comprises a channel area 5 formed in a semiconductor substrate; a source 1 formed adjacent to the channel area 5 in the semiconductor substrate; a drain 3 formed opposite the source l with the channel area 5 therebetween in the semiconductor substrate, the drain 3 being connected to a bit line; a tunnel oxide film 7 formed on the channel area 5, the tunnel oxide film 7 having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate 9 formed on the tunnel oxide film 7 so as not to overlap either the source 1 nor the drain 3; a gate insulating film 10 formed over the floating gate 9; and a control gate 11 formed on the gate insulating film 10 so as to partially overlap both of the source 1 and the drain 3, the control gate 11 being connected to a word line.
As described above, the DTM is a memory using the floating gate 9 similar to a flash memory, with the tunnel oxide film 7 having a thickness thinned down to approximately 2 nm between the channel area 5 and the floating gate 9. It is noted that a tunnel oxide film for a normal flash memory has a thickness of approximately 10 nm.
As a result of the tunnel oxide film 7 having such a reduced thickness, the DTM enables writing or erasing data at high speed with a low voltage. On the other hand, the tunnel oxide film 7 having a reduced thickness may cause a problem of a reduced data-hold property. However, the DTM secures a data-hold time by having the structure in which the floating gate 9 does not overlap either the source 1 nor the drain 3.
FIG. 2 is an illustration for explaining a structure and writing operations of a conventional NOR-type DTM cell array. As shown in FIG. 2, each of memory cells 13a to 13d composing the NOR-type DTM cell array has a gate (the control gate 11) connected to a word line either 15 or 17; and a source (the source 1) and a drain (the drain 3) connected to a pair of bit lines 19 and 21, respectively, or a pair of bit lines 23 and 25, respectively.
Then, when the memory cell 13a is selected as an object to write data in, a voltage VW0 of the word line 15 is made a voltage VP of 4V, and a voltage VW1 of the word line 17 is made 0V. Also, a voltage VBS0 of the bit line 19 and a voltage VBD0 of the bit line 21 are made 0V, and a voltage VBS1 of the bit line 23 and a voltage VBD1 of the bit line 25 are made the voltage VP of 4V.
Accordingly, the control gate 11 of the memory cell 13a has a higher electric potential than the source 1 and the drain 3. Thereby, electrons are accumulated in the floating gate 9 so that data of xe2x80x9c1xe2x80x9d is written in the memory cell 13a. In this course, in the NOR-type DTM cell array shown in FIG. 2, since a source voltage supplied to the memory cells 13a and 13c included in the selected column and a source voltage supplied to the memory cells 13b and 13d included in the unselected column are different, a source line cannot commonly be used to supply a source voltage. This disadvantageously increases a size of the cell.
Next, when data is read from the memory cell 13a in the NOR-type DTM cell array, the voltage VW0 of the word line 15 is made a voltage VR of 2V, and the voltage VW1 of the word line 17 is made 0V, as shown in FIG. 3. Also, the voltage VBS0 of the bit line 19 is made 0V, and the voltage VBD0 of the bit line 21 is made a voltage VD of 1V. Further, the voltage VBS1 of the bit line 23 and the voltage VBD1 of the bit line 25 are made 0V.
Thereby, a change of a threshold voltage of the memory cell 13a is detected so that the data is read out.
Next, when data included in a cell area 27 shown in FIG. 4 are erased all at once in the NOR-type DTM cell array, the voltage VW0 of the word line 15 is made a voltage VE of xe2x88x924V, and the voltage VW1 of the word line 17 is made 0V. Also, the voltage VBS0 of the bit line 19 and the voltage VBD0 of the bit line 21 are made 0V. Further, the voltage VBS1 of the bit line 23 and the voltage VBD1 of the bit line 25 are also made 0V.
Thereby, electrons are extracted from the floating gate 9 of each of the memory cells included in the cell area 27 to the channel area 5, erasing the data all at once. In this erasing method, there is a disadvantage that all data included in the memory cells connected to the word line 15 are inevitably erased, making the NOR-type DTM cell array unusable for a random access memory.
In addition, when data is held in the memory cell in the NOR-type DTM cell array, the voltage VW0 of the word line 15 and the voltage VW1 of the word line 17 are made 0V as shown in FIG. 5. Also, the voltage VBS0 of the bit line 19 and the voltage VBD0 of the bit line 21 are made 0V. Further, the voltage VBS1 of the bit line 23 and the voltage VBD1 of the bit line 25 are also made 0V.
It is a general object of the present invention to provide an improved and useful semiconductor memory device and a controlling method thereof in which device and method the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device and a controlling method thereof which device can operate at high speed, has small-sized memory cells, and is randomly accessible.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, each of the memory cells comprising:
a source area formed adjacent to a channel area in the semiconductor substrate;
a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines;
a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon;
a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area;
a gate insulating film formed on the floating gate so as to cover the floating gate: and a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines,
wherein the source areas of the memory cells are connected to each other so that a common voltage is supplied to each of the source areas.
According to the present invention, source electrodes can be made common, reducing the sizes of the memory cell and the semiconductor memory device including the memory cells.
Additionally, the semiconductor memory device according to the present invention further comprises:
an erase-voltage generating circuit supplying a first voltage to one of the bit lines connected to selected one of the memory cells, the first voltage being lower than voltages supplied to the others of the bit lines and the common voltage; and
a write-voltage generating circuit supplying a second voltage to one of the word lines connected to the selected one of the memory cells, the second voltage being higher than voltages supplied to the others of the word lines and the common voltage.
Additionally, in the semiconductor memory device according to the present invention, the first voltage may be lower than a substrate voltage supplied to the semiconductor substrate.
According to the present invention, electrons can be injected to the floating gate.
On the other hand, in the semiconductor memory device according to the present invention, the write-voltage generating circuit can supply a third voltage to one of the bit lines connected to selected one of the memory cells, the third voltage being higher than voltages supplied to the others of the bit lines and the common voltage, and
the erase-voltage generating circuit can supply a fourth voltage to one of the word lines connected to the selected one of the memory cells, the fourth voltage being lower than voltages supplied to the others of the word lines and the common voltage.
According to the present invention, electrons can be extracted from the floating gate of the selected memory cell in a cell-by-cell manner. Accordingly, there is provided a semiconductor memory device that is randomly accessible and is capable of writing and erasing data at high speed.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a method of controlling a semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, each of the memory cells comprising:
a source area formed adjacent to a channel area in the semiconductor substrate;
a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines;
a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon;
a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area;
a gate insulating film formed on the floating gate so as to cover the floating gate; and
a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines, the method comprising the step of:
supplying a common voltage to the source areas of the memory cells connected to each other.
According to the present invention, source electrodes can be made common so that the size of the memory cell is reduced. This also miniaturizes the semiconductor memory device including the memory cells.
Additionally, the method of controlling the semiconductor memory device according to the present invention further comprises:
a first step of supplying a first voltage to one of the bit lines connected to selected one of the memory cells, the first voltage being lower than voltages supplied to the others of the bit lines and the common voltage; and
a second step of supplying a second voltage to one of the word lines connected to the selected one of the memory cells, the second voltage being higher than voltages supplied to the others of the word lines and the common voltage.
Additionally, in the method of controlling the semiconductor memory device according to the present invention, the first step of supplying may include the step of supplying the first voltage lower than a substrate voltage supplied to the semiconductor substrate.
According to the present invention, electrons can be injected to the floating gate.
Additionally, in the method of controlling the semiconductor memory device according to the present invention, the second step of supplying may include the step of turning off the others of the memory cells by supplying a voltage to all of the word lines except the selected word line.
According to the present invention, the unselected memory cells are kept from turning on. This avoids increasing an amount of electric power consumed in writing data.
On the other hand, the method of controlling the semiconductor memory device according to the present invention further comprises the steps of:
supplying a first voltage to one of the bit lines connected to selected one of the memory cells, the first voltage being higher than voltages supplied to the others of the bit lines and the common voltage, and
supplying a second voltage to one of the word lines connected to the selected one of the memory cells, the second voltage being lower than voltages supplied to the others of the word lines and the common voltage.
According to the present invention, electrons can be extracted from the floating gate of the selected memory cell in a cell-by-cell manner. Accordingly, there is provided a semiconductor memory device that is randomly accessible and is capable of writing and erasing data at high speed.